Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes
AT91SAM9M10-G45-EK
Page of 1361
 1185
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
 
46.8.2
Decoder  Interrupt  Register
Name:
VDEC_DIR
Address:
0x00900004
Access:
Read-write
• DE:  Decoder  Enable
0: Disables decoder.
1: Enables decoder.
Setting this bit high will start the decoding operation. Hardware will reset this bit when a picture is processed, a stream error
or ASO is detected or a bus error is received.
• ID:  Interrupt  Disable
0: Enables interrupts for decoder.
1: Disables interrupts for decoder.
When high, there will be no interrupts issued by the decoder. Polling must be used to see the hardware status.
• ISET:  Decoder  Interrupt  Set
0: Clears the decoder interrupt.
Software will reset this after the interrupt is handled.
1: Sets the decoder interrupt.
This bit drives the interrupt line, OR gated with the post-processor interrupt bit. The interrupt line is not used for the decoder
if the interrupt disable bit for decoder is high.
• DR:  Decoder  Ready
0: Decoding in progress.
1: Decoder is ready.
When high, the hardware has decoded a picture. Hardware will self-reset.
• BE:  Bus  Error
0: No error.
1: A bus error has occurred.
When high, hardware has received an error response from the bus while accessing external memory. This is a fatal error
possibly caused by the incorrect allocation of decoder linear memory. Hardware will self-reset.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TO
JPEGSD
ISE
15
14
13
12
11
10
9
8
ASOD
SBE
BE
DR
ISET
7
6
5
4
3
2
1
0
ID
DE