Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
130
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
.
summarizes the Slave Memory Mapping for each connected Master, depending on the Remap status
(RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and the BMS state at reset.
19.3
Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master sev-
eral memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash,
etc.) becomes possible.
eral memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash,
etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap
action for every master independently.
action for every master independently.
19.4
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
some masters. This mechanism reduces latency at first access of a burst or single transfer as long as the slave is
free from any other master access, but does not provide any benefit as soon as the slave is continuously accessed
by more than one master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or
access latency.
some masters. This mechanism reduces latency at first access of a burst or single transfer as long as the slave is
free from any other master access, but does not provide any benefit as soon as the slave is continuously accessed
by more than one master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or
access latency.
This bus granting mechanism sets a different default master for every slave.
Table 19-4.
SAM9M10 Masters to Slaves Access with VDEC_SEL = 1 (default)
Master
0
1
2
3
4 & 5
6
7
8
9
10
11
Slave
ARM
926
Instr.
ARM
926
Data
PDC
USB
HOST
OHCI
DMA
ISI
DMA
LCD
DMA
Ethern
et MAC
USB
Device
HS
USB
Host
EHCI
VDEC
0
Internal SRAM 0
X
X
X
X
X
X
-
X
X
X
-
1
Internal ROM
X
X
X
-
-
-
-
-
X
-
-
UHP OHCI
X
X
-
-
-
-
-
-
-
-
-
UHP EHCI
X
X
-
-
-
-
-
-
-
-
-
LCD User Int.
X
X
-
-
-
-
-
-
-
-
-
UDPHS RAM
X
X
-
-
-
-
-
-
-
-
-
VDEC
X
X
-
-
-
-
-
-
-
-
-
2
DDR Port 0
-
-
-
-
-
-
-
-
-
-
X
3
DDR Port 1
-
-
-
-
-
-
X
-
-
-
-
4
DDR Port 2
X
-
X
X
X
X
-
X
X
X
-
5
DDR Port 3
-
X
X
X
X
X
-
X
X
X
-
6
EBI
X
X
X
X
X
X
X
X
X
X
X
7
Internal Periph.
X
X
X
-
X
-
-
-
-
-
-
Table 19-5.
Internal Memory Mapping
Master
Slave
Base Address
RCBx
= 0
RCBx = 1
BMS = 1
BMS
= 0
0x0000 0000
Internal ROM
EBI NCS0
Internal SRAM