Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
1333
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
50. SAM9M10 Errata
50.1
SAM9M10 Errata - Rev. A Parts
50.1.1
Boot ROM
50.1.1.1
Boot ROM: NAND Flash boot does not support ECC Correction
The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not
feature ECC correction on a NAND Flash.
feature ECC correction on a NAND Flash.
Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free. Therefore we advise to
locate the bootstrap program into another device supported by the boot ROM (DataFlash, Serial Flash, SDCARD
or EEPROM), and to implement a NAND Flash access with ECC.
locate the bootstrap program into another device supported by the boot ROM (DataFlash, Serial Flash, SDCARD
or EEPROM), and to implement a NAND Flash access with ECC.
Problem Fix/Workaround
None.
50.1.1.2
Boot ROM: Boot issue on AT45-series SPI dataflash
The boot from AT45-series SPI DataFlash is not functional except for the AT45DB321D. Future revisions of the
AT45DB321D might not be functional either.
AT45DB321D might not be functional either.
Problem Fix/Workaround
Use AT25-series serial Flash instead.
50.1.2
EMAC
50.1.2.1
EMAC: Setup Timing Violation in RMII Mode
A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V]
and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V].
and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V].
Problem Fix/Workaround
None.
50.1.3
Error Corrected Code Controller (ECC)
50.1.3.1
ECC: Computation with a 1 clock cycle long NRD/NWE pulse
If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, ECC cannot compute the parity.
Problem Fix/Workaround
It is recommended to program SMC with a value superior to 1.
50.1.3.2
Incomplete parity status when error in ECC parity
When a single correctable error is detected in ECC value, the error is located in ECC Parity register's field which
contains a 1 in the 24 least significant bits except when the error is located in the 12th or the 24th bit. In this case,
these bits are always stuck at 0.
contains a 1 in the 24 least significant bits except when the error is located in the 12th or the 24th bit. In this case,
these bits are always stuck at 0.
A Single correctable error is detected but it is impossible to correct it.
Problem Fix/Workaround
None.
50.1.3.3
Unsupported ECC per 512 words
1 bit ECC per 512 words is not functional.
Problem Fix/Workaround