Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 1342

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

It is impossible to update a period equal to 0 by using the PWM_CUPD register.

None

When a software reset (CPU and peripherals) occurs during DDRAM read access, the CPU will stop the DDRAM
clock.

The DDRAM maintains the data on the bus until the clock restarts. This will create a bus conflict if another memory,
sharing the external bus with the DDRAM, is accessed prior to completion of the read access to the DDRAM. Such
a conflict will occur when the device boots out of an external NAND or NOR Flash following a software reset.

1) Boot from serial Flash

2) Before generating the software reset, the user must ensure that all the accesses to DDRAM are completed and
then put the DDRAM in self-refresh mode. The routine to generate the software reset must be located in internal
SRAM or in the ARM cache memory.

In this document, the Access is “Read-write” in the Register Mapping Table (SMC_DELAY1 to SMC_DELAY8
rows), and in the SMC DELAY I/O Register.

The current access is “Write-only”.

None

When SSC is configured with the following conditions:

• RF is in input,

• TD is synchronized on a receive START (any condition: START field = 2 to 7)

• TF toggles at each start of data transfer

• Transmit STTDLY = 0

• Check TD and TF after a receive START,

The data is sent but there is not any toggle of the TF line 

Transmit STTDLY must be different from 0.

When SSC is configured with the following conditions:

• TCMR.STTDLY more than 0