Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

the NAND Flash logic.

 

For details on this register, refer to the Bus Matrix Section. Access to an external NAND

Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and
0x4FFF FFFF).

The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE
signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address
fails to lie in the NCS3 address space. See 

 for more information. For details on these

waveforms, refer to the Static Memory Controller section.

The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits
A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash
device are distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the
device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even
when NCSx is not selected, preventing the device from returning to standby mode.

NAND Flash Application Example

The following hardware configurations are given for illustration only. The user should refer to the memory manufac-
turer web site to check current device availability.

D[7:0]

ALE

NANDWE

NANDOE

NOE

NWE

A[22:21]

CLE

AD[7:0]

PIO

R/B

EBI

CE

NAND Flash

PIO

NCSx/NANDCS

Not Connected