Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 179

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

• The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes. 

• A21, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated 

PIOs must be programmed in peripheral mode in the PIO controller.

• Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT 

functions respectively.

• Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to 

CompactFlash timings and system bus frequency.

The power supply pin VDDIOM1 accepts two voltage ranges. This allows the device to reach its maximum speed
either out of 1.8V or 3.3V external memories.

The maximum speed is 133 MHz on the SDCK pin and #SDCK signals loaded with 10 pF. The load on
data/address and control signals are 30 pF for power supply at 1.8V and

50 pF

for power supply at 3.3V. The data

lines frequency reaches 133 MHz in DDR2 mode. The other signals (control and address) do not go over 66 MHz.

The EBI I/Os accept two drive levels, HIGH and LOW. This allows to avoid overshoots and give the best perfor-
mance according to the bus load and external memories. Refer to the EBI Chip Select Assignment Register for
more details.

The voltage ranges and the drive level are determined by programming EBI_DRIVE field in the Chip Configuration
registers located in the Matrix User Interface.

At reset the selected default drive level is High. 

At reset, the selected voltage defaults to 3.3V typical and power supply pins can accept either 1.8V or 3.3V. The
user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. The
user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode.