Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
183
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
21.6
External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of
memory.
memory.
If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and
appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within
the page (see
appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within
the page (see
).
A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory.
Figure 21-2.
Memory Connections for Eight External Devices
21.7
Connection to External Devices
21.7.1
Data Bus Width
A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW
in SMC_MODE (Mode Register) for the corresponding chip select.
in SMC_MODE (Mode Register) for the corresponding chip select.
shows how to connect a 512K x 8-bit memory on NCS2.
16-bit memory on NCS2.
21.7.2
Byte Write or Byte Select Access
Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte
write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding
chip select.
write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding
chip select.
NRD
NWE
A[25:0]
D[31:0]
8 or 16 or 32
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[25:0]
D[31:0] or D[15:0] or
D[7:0]
D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS7
NCS4
NCS5
NCS6
NCS[0] - NCS[7]
SMC