Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
216
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
21.15 Static Memory Controller (SMC) User Interface
The SMC is programmed using the registers listed in
16 bytes (0x10) are required per chip select.
The user must complete writing the configuration by writing any one of the SMC_MODE registers.
Table 21-8.
Register Mapping
Offset
Register
Name
Access
Reset
0x10 x CS_number + 0x00
SMC Setup Register
SMC_SETUP
Read-write
0x01010101
0x10 x CS_number + 0x04
SMC Pulse Register
SMC_PULSE
Read-write
0x01010101
0x10 x CS_number + 0x08
SMC Cycle Register
SMC_CYCLE
Read-write
0x00030003
0x10 x CS_number + 0x0C
SMC Mode Register
SMC_MODE
Read-write
0x10001000
0xC0
SMC Delay on I/O
SMC_DELAY1
Read-write
0x00000000
0xC4
SMC Delay on I/O
SMC_DELAY2
Read-write
0x00000000
0xC8
SMC Delay on I/O
SMC_DELAY3
Read-write
0x00000000
0xCC
SMC Delay on I/O
SMC_DELAY4
Read-write
0x00000000
0xD0
SMC Delay on I/O
SMC_DELAY5
Read-write
0x00000000
0xD4
SMC Delay on I/O
SMC_DELAY6
Read-write
0x00000000
0xD8
SMC Delay on I/O
SMC_DELAY7
Read-write
0x00000000
0xDC
SMC Delay on I/O
SMC_DELAY8
Read-write
0x00000000
0xEC-0xFC
Reserved
-
-
-