Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
23
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
8.3
Peripheral Interrupts and Clock Control
8.3.1
System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the DDR2/LPDDR Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-Time Timer
• the Real-Time Clock
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced
Interrupt Controller.
Interrupt Controller.
8.3.2
External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a dedicated Periph-
eral ID. However, there is no clock control associated with these peripheral IDs.
eral ID. However, there is no clock control associated with these peripheral IDs.
8.4
Peripheral Signals Multiplexing on I/O Lines
The SAM9M10 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplexes the I/O lines of
the peripheral set.
the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B.
The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multi-
plexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for
the user’s own comments; they may be used to track how pins are defined in an application.
The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multi-
plexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for
the user’s own comments; they may be used to track how pins are defined in an application.
Note that some peripheral function which are output only, might be duplicated within the both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is men-
tioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as
soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Periph-
eral Status Register) resets low.
tioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as
soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Periph-
eral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corre-
sponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines,
which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in
this case.
sponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines,
which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in
this case.
To amend EMC, programmable delay has been inserted on PIO lines able to run at high speed.