Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
245
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
22.5.5
Multi-port Functionality
The SDRAM protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the
performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a
row in a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must
be performed to open a bank: Precharge and Active command with respect to Trp timing. Before performing a read
or write command, Trcd timing must checked.
performance of systems. An access to SDRAM is performed if banks and rows are open (or active). To activate a
row in a particular bank, it has to de-active the last open row and open the new row. Two SDRAM commands must
be performed to open a bank: Precharge and Active command with respect to Trp timing. Before performing a read
or write command, Trcd timing must checked.
This operation represents a significative loss. (see
).
Figure 22-24.
Trp and Trcd Timings
The multi-port controller has been designed to mask these timings and thus improve the bandwidth of the system.
DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller. This feature
improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus antic-
ipate the commands that follow, PRECHARGE and ACTIVE commands in bank X during current access in bank Y.
This allows Trp and Trcd timings to be masked (see
improves the bandwidth of the system because it can detect four requests on the AHB slave inputs and thus antic-
ipate the commands that follow, PRECHARGE and ACTIVE commands in bank X during current access in bank Y.
This allows Trp and Trcd timings to be masked (see
). In the best case, all accesses are done as if the
banks and rows were already open. The best condition is met when the four masters work in different banks. In the
case of four simultaneous read accesses, when the four banks and associated rows are open, the controller reads
with a continuous flow and masks the cas latency for each different access. To allow a continuous flow, the read
command must be set at 2 or 3 cycles (cas latency) before the end of current access. This requires that the
scheme of arbitration changes since the round-robin arbitration cannot be respected. If the controller anticipates a
read access, and thus before the end of current access a master with a high priority arises, then this master will not
serviced.
case of four simultaneous read accesses, when the four banks and associated rows are open, the controller reads
with a continuous flow and masks the cas latency for each different access. To allow a continuous flow, the read
command must be set at 2 or 3 cycles (cas latency) before the end of current access. This requires that the
scheme of arbitration changes since the round-robin arbitration cannot be respected. If the controller anticipates a
read access, and thus before the end of current access a master with a high priority arises, then this master will not
serviced.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the
SDRAM device at the same time.
SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from different masters to the
SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the
lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and
to provide the maximum throughput for the SDRAM device, arbitration may only take place during the following
cycles:
SDRAM device in a round-robin manner. If two or more master requests arise at the same time, the master with the
lowest number is serviced first, then the others are serviced in a round-robin manner. To avoid burst breaking and
to provide the maximum throughput for the SDRAM device, arbitration may only take place during the following
cycles:
NOP
PRCHG
NOP
ACT
NOP
READ
BST
NOP
0
3
Trp
Trcd
Latency =2
4 cycles before performing a read command
SDCLK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
D[15:0]
DM1:0]
Da
Db