Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes

AT91SAM9M10-G45-EK

259

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

22.8.5

DDRSDRC Timing Parameter 1 Register

Name:

DDRSDRC_TPR1

Address:

0xFFFFE610 (0), 0xFFFFE410 (1)

Access:

Read-write

Reset:

See

Table 22-8

This register can only be written if the bit WPEN is cleared in

“DDRSDRC Write Protect Mode Register” on page 267

• TRFC: Row Cycle Delay

Reset Value is 8 cycles.

This field defines the delay between a Refresh and an Activate command or Refresh command in number of cycles. Num-
ber of cycles is between 0 and 31

• TXSNR: Exit Self Refresh Delay to Non-read Command

Reset Value is 8 cycles.

This field defines the delay between cke set high and a non Read Command in number of cycles. Number of cycles is
between 0 and 255. This field is used for SDR-SDRAM and DDR-SDRAM devices. In the case of SDR-SDRAM devices
and Low-power DDR1-SDRAM, this field is equivalent to TXSR timing.

• TXSRD: ExiT Self Refresh Delay to Read Command

Reset Value is 200 cycles.

This field defines the delay between cke set high and a Read Command in number of cycles. Number of cycles is between
0 and 255 cycles.This field is unique to DDR-SDRAM devices. In the case of a Low-power DDR1-SDRAM, this field must
be written to 0.

• TXP: Exit Power-down Delay to First Command

Reset Value is 3 cycles.

This field defines the delay between cke set high and a Valid Command in number of cycles. Number of cycles is between
0 and 15 cycles. This field is unique to Low-power DDR1-SDRAM devices and DDR2-SDRAM devices.

–

TXP

TXSRD

TXSNR

–

TRFC