Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 311

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip
memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge.

The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user
interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two
16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The
bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set
(pointer, counter) is used by current transmit, next transmit, current receive and next receive. 

Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly
reduces the number of clock cycles required for a data transfer, which improves microcontroller performance.

To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals.
When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.

• Acting as one AHB Bus Matrix Master 

• Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.

• Next Pointer support, prevents strong real-time constraints on buffer management.

The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities
(Low to High priorities):

Peripheral DMA Controller 

DBGU

Transmit

USART3

Transmit

USART2

Transmit

USART1

Transmit

USART0

Transmit

AC97C

Transmit

SPI1

Transmit

SPI0

Transmit

SSC1

Transmit

SSC0

Transmit

TSADCC

Receive

DBGU

Receive

USART3

Receive

USART2

Receive

USART1

Receive

USART0

Receive

AC97C

Receive

SPI1

Receive