Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
338
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
26.10 Clock Switching Details
26.10.1
Master Clock Switching Timings
one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64
clock cycles of the new selected clock has to be added.
clock cycles of the new selected clock has to be added.
26.10.2
Clock Switching Waveforms
Figure 26-3.
Switch Master Clock from Slow Clock to PLLA Clock
Table 26-1.
Clock Switching Timings (Worst Case)
From
Main Clock
SLCK
PLLA Clock
To
Main Clock
–
4 x SLCK +
2.5 x Main Clock
3 x PLLA Clock +
4 x SLCK +
1 x Main Clock
SLCK
0.5 x Main Clock +
4.5 x SLCK
–
3 x PLLA Clock +
5 x SLCK
PLLA Clock
0.5 x Main Clock +
4 x SLCK +
PLLACOUNT x SLCK +
2.5 x PLLAx Clock
2.5 x PLLA Clock +
5 x SLCK +
PLLACOUNT x SLCK
2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLL Clock