Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
399
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
1.
The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link
register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch
at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.
register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch
at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four.
2.
The ARM core enters Interrupt mode, if it has not already done so.
3.
When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value
read in AIC_IVR. Reading the AIC_IVR has the following effects:
read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current
level is the priority level of the current interrupt.
– De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in
order to de-assert nIRQ.
– Automatically clears the interrupt, if it has been programmed to be edge-triggered.
– Pushes the current level and the current interrupt number on to the stack.
– Returns the value written in the AIC_SVR corresponding to the current interrupt.
4.
The previous step has the effect of branching to the corresponding interrupt service routine. This should
start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four
when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For
example, the instruction
start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four
when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For
example, the instruction
SUB PC, LR, #4
may be used.
5.
Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ
to be taken into account by the core. This can happen if an interrupt with a higher priority than the current
interrupt occurs.
to be taken into account by the core. This can happen if an interrupt with a higher priority than the current
interrupt occurs.
6.
The interrupt handler can then proceed as required, saving the registers that will be used and restoring
them at the end. During this phase, an interrupt of higher priority than the current level will restart the
sequence from step 1.
them at the end. During this phase, an interrupt of higher priority than the current level will restart the
sequence from step 1.
Note:
If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7.
The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is
completed in an orderly manner.
completed in an orderly manner.
8.
The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that
the current interrupt is finished. This causes the current level to be popped from the stack, restoring the
previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority
than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted,
but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is
restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of
returning from the interrupt to whatever was being executed before, and of loading the CPSR with the
stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.
the current interrupt is finished. This causes the current level to be popped from the stack, restoring the
previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority
than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted,
but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is
restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of
returning from the interrupt to whatever was being executed before, and of loading the CPSR with the
stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.
Note:
The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt
when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (inter-
rupt is masked).
when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (inter-
rupt is masked).
28.8.4
Fast Interrupt
28.8.4.1
Fast Interrupt Source
The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forc-
ing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a
PIO Controller.
ing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a
PIO Controller.
28.8.4.2
Fast Interrupt Control
The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the
AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRC-
TYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge
triggered or high-level sensitive or low-level sensitive
AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRC-
TYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge
triggered or high-level sensitive or low-level sensitive