Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
417
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
29.4
Product Dependencies
29.4.1
I/O Lines
Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the pro-
grammer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
grammer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
29.4.2
Power Management
Depending on product integration, the Debug Unit clock may be controllable through the Power Management Con-
troller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the
peripheral identifier used for this purpose is 1.
troller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the
peripheral identifier used for this purpose is 1.
29.4.3
Interrupt Source
Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug
Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with
the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in
Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug
Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with
the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in
29.5
UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with
parity). It has no clock pin.
parity). It has no clock pin.
The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common
baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the imple-
mented features are compatible with those of a standard USART.
baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the imple-
mented features are compatible with those of a standard USART.
29.5.1
Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the
transmitter.
transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate
Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART
remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud
rate is Master Clock divided by (16 x 65536).
Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART
remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud
rate is Master Clock divided by (16 x 65536).
Table 29-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
DBGU
DRXD
PB12
A
DBGU
DTXD
PB13
A
Baud Rate
MCK
16
CD
×
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