Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
482
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 31-10.
Start Frame Delimiter
31.7.3.3
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock
drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X
clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the
RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one
clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is
lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automati-
cally taken.
drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X
clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the
RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one
clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is
lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automati-
cally taken.
Figure 31-11.
Bit Resynchronization
31.7.3.4
Asynchronous Receiver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD
input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode
Register (US_MR).
input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode
Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected
and data, parity and stop bits are successively sampled on the bit rate clock.
and data, parity and stop bits are successively sampled on the bit rate clock.
Manchester
encoded
data
Txd
SFD
DATA
One bit start frame delimiter
Preamble Length
is set to 0
Manchester
encoded
data
Txd
SFD
DATA
Command Sync
start frame delimiter
Manchester
encoded
data
Txd
SFD
DATA
Data Sync
start frame delimiter
RXD
Oversampling
16x Clock
Sampling
point
Expected edge
Tolerance
Synchro.
Jump
Sync
Jump
Synchro.
Error
Synchro.
Error