Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes
AT91SAM9M10-G45-EK
Page of 1361
 494
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
 
Figure  31-26.
Break Transmission
31.7.3.15
Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data at 0x00, but FRAME remains low. 
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writ-
ing the Control Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode
or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK
bit.
31.7.3.16
Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to con-
nect with the remote device, as shown in 
Figure  31-27.
Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the
Mode Register (US_MR) to the value 0x2. 
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchro-
nous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the
CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC
channel for reception. The transmitter can handle hardware handshaking in any case.
 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if
the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Nor-
mally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the
Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buf-
fer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start 
Bit
Parity
Bit
Stop
Bit
Baud Rate
 Clock
Write
US_CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1 
Break Transmission
End of Break
USART
TXD
CTS
Remote 
Device
RXD
TXD
RXD
RTS
RTS
CTS