Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 572

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The read mode is defined as a data requirement from the master.

After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave
address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.

Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR
register.

If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.

 describes the write operation.

Read Access Ordered by a MASTER

Notes:

1. When SVACC is low, the state of SVREAD becomes irrelevant.

2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been 

acknowledged or non acknowledged.

The write mode is defined as a data transmission from the master.

After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded,
SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).

Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register.

If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.

 describes the Write operation.

Write THR

Read RHR

SVREAD has to be taken into account only while SVACC is active

TWD

TXRDY

NACK

SVACC

SVREAD

EOSVACC

SADR

S

ADR

R

NA

R

A

DATA

A

A

DATA

NA

S/Sr

DATA

NA

P/S/Sr

SADR matches,

TWI answers with an ACK

SADR does not match,

TWI answers with a NACK

ACK/NACK from the Master