Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was
not detected, it is tied low until TWI_RHR is read.

 describes the clock synchronization in Read mode.

Clock Synchronization in Write Mode

Notes:

1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from 

SADR.

2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-

nism is finished.

Rd DATA0

Rd DATA1

Rd DATA2

SVACC

SVREAD

RXRDY

SCLWS

TXCOMP

DATA1

DATA2

SCL is stretched on the last bit of DATA1

As soon as a START is detected

TWCK

TWD

TWI_RHR

CLOCK is tied low by the TWI as long as RHR is full

DATA0 is not read in the RHR

ADR

S

SADR

W

A

DATA0

A

A

DATA2

DATA1

S

NA