Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 600

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Divided Clock Block Diagram  

The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is
4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is
provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used
and remains inactive.

When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by
2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a
50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.

 Divided Clock Generation 

The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the
TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register).
Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR.

The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock out-
put is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock
outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit
Clock (CKO field) might lead to unpredictable results.

MCK

Divided Clock

Clock Divider

/ 2

12-bit Counter

SSC_CMR

Master Clock

Divided Clock

DIV = 1

Master Clock

Divided Clock

DIV = 3

Divided Clock Frequency = MCK/2

Divided Clock Frequency = MCK/6

MCK / 2

MCK / 8190