Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 689

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

– SRC_INCR is set to INCR.

– FC field is programmed with peripheral to memory flow control mode.

– Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor location 

points to 0.

– DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is able 

to prefetch data and write HSMCI simultaneously.

p.

Program LLI_B(n).DMAC_CFGx memory location for channel x with the following field’s values:

– FIFOCFG defines the watermark of the DMAC channel FIFO.

– SRC_H2SEL is set to true to enable hardware handshaking on the destination.

– SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host Controller

q.

Program LLI_B(n).DMAC_DSCR with address of descriptor LLI_W(n+1). If LLI_B(n) is the last 
descriptor, then program LLI_B(n).DMAC_DSCR with 0.

r.

Program DMAC_CTRLBx register for channel x with 0, its content is updated with the LLI Fetch 
operation.

s.

Program DMAC_DSCRx with the address of LLI_W(0) if 

is greater than 4 else with 

address of LLI_B(0).

t.

Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.

4.

Enable DMADONE interrupt in the HSMCI_IER register.

5.

Poll CBTC[x] bit in the DMAC_EBCISR Register.

6.

If a new list of buffers shall be transferred, repeat step 7. Check and handle HSMCI errors.

7.

Poll FIFOEMPTY field in the HSMCI_SR.

8.

Send The STOP_TRANSMISSION command writing HSMCI_ARG then HSMCI_CMDR.

9.

Wait for XFRDONE in HSMCI_SR register.

One DMA Transfer descriptor is used to perform the HSMCI block transfer, the DMA writes a rounded up value to
the nearest multiple of 4.

1.

Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK.

2.

Set the ROPT field to 1 in the HSMCI_DMA register.

3.

Issue a READ_MULTIPLE_BLOCK command.

4.

Program the DMA controller to use a list of descriptors:

a.

Read the channel Register to choose an available (disabled) channel.

b.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the 
DMAC_EBCISR register.

c.

Program the channel registers in the Memory with the first descriptor. This descriptor will be word ori-
ented. This descriptor is referred to as LLI_W(n), standing for LLI word oriented transfer for block 

.

d.

The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting address of the 
HSMCI_FIFO address.

e.

The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.

f.

Program LLI_W(n).DMAC_CTRLAx with the following field’s values:

–DST_WIDTH is set to WORD.

–SRC_WIDTH is set to WORD.

–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.

–BTSIZE is programmed with