Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Several methods of ATA command failure may occur, including:

• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).

• CRC is invalid for an MMC command or response.

• CRC16 is invalid for an MMC data packet.

• ATA Status register reflects an error by setting the ERR bit to one.

• The command completion signal does not arrive within a host specified time out period.

Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism may be used for
each error event. The recommended error recovery procedure after a timeout is:

• Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK 

(CMD61) response has been received.

• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.

• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).

If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if
the error recovery procedure does not work as expected or there is another timeout, the next step is to issue
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely
resets all device states.

Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-
ATA device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA
Status register, no error recovery action is required. The ATA command itself failed implying that the device could
not complete the action requested, however, there was no communication or protocol failure. After the device sig-
nals an error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command.

In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line
low after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending
on register setting.

1.

Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR register. The 
BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly.

2.

Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and 
BCNT fields of the HSMCI_BLKR Register.

3.

Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCMD field 
set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.

4.

The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the BOOT_ACK field of 
the MMC device located in the Extended CSD register is set to one.

5.

Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted.

6.

When Data transfer is completed, host processor shall terminate the boot stream by writing the 
HSMCI_CMDR register with SPCMD field set to BOOTEND.