Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral
Reset are asserted. 

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with
the value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock
cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH
because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. 

User Reset State

SLCK

periph_nreset

proc_nreset

NRST

NRST

(nrst_out)

>= EXTERNAL RESET LENGTH

MCK

Processor Startup 

= 3 cycles

Any

Freq.

Resynch.

2 cycles

RSTTYP

Any

XXX

Resynch.

2 cycles

0x4 = User Reset