Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 732

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error
is indicated and no further attempts are made if 16 attempts cause collisions.

If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and
the tx_er signal is asserted. For a properly configured system, this should never happen.

If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64
bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame
to force a collision. This provides a way of implementing flow control in half-duplex mode.

The start of an 802.3 pause frame is as follows:

The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the
pause time register is updated with the frame’s pause time, regardless of its current contents and regardless of the
state of the configuration register bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it
is enabled in the interrupt mask register. If bit 13 is set in the network configuration register and the value of the
pause time register is non-zero, no new frame is transmitted until the pause time register has decremented to zero.

The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is config-
ured for full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the
pause frame received interrupt is still triggered. 

A valid pause frame is defined as having a destination address that matches either the address stored in specific
address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause
opcode of 0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid
pause frames received increment the Pause Frame Received statistic register.

The pause time register decrements every 512 bit times (i.e., 128 

rx_clks

in nibble mode) once transmission

has stopped. For test purposes, the register decrements every 

rx_clk

cycle once transmission has stopped if bit

12 (retry test) is set in the network configuration register. If the pause enable bit (13) is not set in the network con-
figuration register, then the decrementing occurs regardless of whether transmission has stopped or not.

An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the
interrupt mask register). 

The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA
block and stores the frames destination address for use by the address checking block. If, during frame reception,
the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block. The DMA
block then ceases sending data to memory. At the end of frame reception, the receive block indicates to the DMA
block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame was bad.
The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame,
long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics.

The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of
up to 10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by
default. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are
discarded.

Start of an 802.3 Pause Frame

0x0180C2000001

6 bytes

0x8808

0x0001

2 bytes