Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
736
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved
value of 0x0000 for the Wake-on-LAN target address value does not cause an ARP request event, even if matched
by the frame.
value of 0x0000 for the Wake-on-LAN target address value does not cause an ARP request event, even if matched
by the frame.
A specific address 1 filter match event occurs if all of the following are true:
•
specific address 1 events are enabled through bit 18 of the
Wake-on-LAN
register
•
the frame’s destination address matches the value programmed in the specific
address 1 registers
A multicast filter match event occurs if all of the following are true:
•
multicast hash events are enabled through bit 19 of the
Wake-on-LAN
register
•
multicast hash filtering is enabled through bit 6 of the network configuration
register
• the frame’s destination address matches against the multicast hash filter
• the frame’s destination address is not a broadcast
36.4.13
PHY Maintenance
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is
used during auto-negotiation to ensure that the EMAC and the PHY are configured for the
used during auto-negotiation to ensure that the EMAC and the PHY are configured for the
same speed and duplex
configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation
which is signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later
when bit ten is set to zero, and bit eleven is set to one in the network configuration register). An interrupt is gener-
ated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from
the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO.
which is signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later
when bit ten is set to zero, and bit eleven is set to one in the network configuration register). An interrupt is gener-
ated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from
the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of management
operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with
data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY manage-
ment frame is produced.
operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with
data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY manage-
ment frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs,
bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration regis-
ter in the
bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration regis-
ter in the
.
36.4.14
Media Independent Interface
The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the EMAC_USRIO reg-
ister controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface
is selected.
ister controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface
is selected.
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u
standard. The signals used by the MII and RMII interfaces are described in
standard. The signals used by the MII and RMII interfaces are described in
Table 36-5.
Pin Configuration
Pin Name
MII
RMII
ETXCK_EREFCK
ETXCK: Transmit Clock
EREFCK: Reference Clock
ECRS
ECRS: Carrier Sense
ECOL
ECOL: Collision Detect
ERXDV
ERXDV: Data Valid
ECRSDV: Carrier Sense/Data Valid
ERX0 - ERX3
ERX0 - ERX3: 4-bit Receive Data
ERX0 - ERX1: 2-bit Receive Data
ERXER
ERXER: Receive Error
ERXER: Receive Error