Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The application is notified that it is possible to write a new packet to the DPR by the TX_PK_RDY interrupt. This
i n t e r r u p t  c a n  b e  e n a b l e d  o r  m a s k e d  b y  s e t t i n g  t h e  T X _ P K _ R D Y  b i t  i n  t h e
UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register.

Algorithm Description to Fill Several Packets:

Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application
overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must
be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register.

The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This
means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is done by hardware.

• The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait 

that at least one bank is free.

• The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time 

the application writes the last byte of a bank, the TX_PK_RDY signal is automatically set by the UDPHS.

• If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the 

TX_PK_RDY bit in the UDPHS_EPTSETSTAx register.

The application is notified that all banks are free, so that it is possible to write another burst of packets by the
BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the
UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers.

This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate.

A Zero Length Packet can be sent by setting just the TX_PKTRDY flag in the UDPHS_EPTSETSTAx register.

The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the mem-
ory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all
transfer types except control transfer.

Example DMA configuration:

1.

Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred.

2.

Enable the interrupt of the DMA in UDPHS_IEN

3.

Program UDPHS_ DMACONTROLx:

– Size of buffer to send: size of the buffer to be sent to the host.

– END_B_EN: The endpoint can validate the packet (according to the values programmed in the 

AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See 

)

– END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0.

– CHANN_ENB: Run and stop at end of buffer

The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This
means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is done by hardware.

A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be pro-
grammed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting
the LDNXT_DSC field (Load Next Descriptor Now) in UDPHS_DMACONTROLx register.

The structure that defines this transfer descriptor must be aligned.

). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS