Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

Product codes
AT91SAM9M10-G45-EK
Page of 1361
 838
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
 
38.6.15
UDPHS  Endpoint  Set  Status  Register
Name:
   UDPHS_EPTSETSTAx 
[x=0..6]
Addresses:
0xFFF78114 [0], 0xFFF78134 [1], 0xFFF78154 [2], 0xFFF78174 [3], 0xFFF78194 [4], 
0xFFF781B4 [5], 0xFFF781D4 [6]
Access:
 Write-only 
• FRCESTALL:  Stall  Handshake  Request  Set
0 = no effect.
1 = set this bit to request a STALL answer to the host for the next handshake
Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the 
Universal Serial Bus Specification, Rev 2.0
 for
more information on the STALL handshake.
• KILL_BANK:  KILL  Bank  Set  (for  IN  Endpoint)
0 = no effect.
1 = kill the last written bank.
• TX_PK_RDY:  TX  Packet  Ready  Set
0 = no effect.
1 = set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host). 
– Device firmware checks that it can write a data payload in the FIFO, checking that TX_PK_RDY is cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting 
TX_PK_RDY to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been received by the host.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TX_PK_RDY
KILL_BANK
7
6
5
4
3
2
1
0
FRCESTALL