Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet
Product codes
AT91SAM9M10-G45-EK
864
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
39.5.1
ISI Configuration 1 Register
Name:
ISI_CFG1
Access:
Read-write
Reset Value:
0x00000000
• HSYNC_POL: Horizontal Synchronization Polarity
0: HSYNC active high.
1: HSYNC active low.
• VSYNC_POL: Vertical Synchronization Polarity
0: VSYNC active high.
1: VSYNC active low.
• PIXCLK_POL: Pixel Clock Polarity
0: Data is sampled on rising edge of pixel clock.
1: Data is sampled on falling edge of pixel clock.
• EMB_SYNC: Embedded Synchronization
0: Synchronization by HSYNC, VSYNC.
1: Synchronization by embedded synchronization sequence SAV/EAV.
• CRC_SYNC: Embedded Synchronization Correction
0: No CRC correction is performed on embedded synchronization.
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in
the status register.
the status register.
• FRATE: Frame Rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
• DISCR: Disable Codec Request
0 = Codec datapath DMA interface requires a request to restart.
1 = Codec datapath DMA automatically restarts.
• FULL: Full Mode is Allowed
0: The codec frame is transferred t memoryu when an available frame slot is detected.
1: Both codec and preview datapaths are working simultaneously.
31
30
29
28
27
26
25
24
SFD
23
22
21
20
19
18
17
16
SLD
15
14
13
12
11
10
9
8
–
THMASK
FULL
DISCR FRATE
7
6
5
4
3
2
1
0
CRC_SYNC
EMB_SYNC
–
PIXCLK_POL
VSYNC_POL
HSYNC_POL
–
–