Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 941

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

f.

If source picture-in-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the 
DMAC_SPIPx register for channel x.

g.

If destination picture-in-picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the 
DMAC_DPIPx register for channel x.

4.

After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the 
DMAC_CHER.ENABLE[n] bit, where n is the channel number. Make sure that bit 0 of 
DMAC_EN.ENABLE register is enabled.

5.

Source and destination request single and chunk DMAC transactions to transfer the buffer of data 
(assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction 
(chunk and single) in the buffer and carry out the buffer transfer.

6.

Once the transfer completes, hardware sets the interrupts and disables the channel. At this time you can 
either respond to the buffer Complete or Transfer Complete interrupts, or poll for the Channel Handler Sta-
tus Register (DMAC_CHSR.ENABLE[n]) bit until it is cleared by hardware, to detect when the transfer is 
complete.

1.

Read the Channel Enable register to choose a free (disabled) channel.

2.

Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control 
information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor 
for each LLI in memory (see 

program the following:

a.

Set up the transfer type (memory or non-memory peripheral for source and destination) and flow con-
trol device by programming the FC of the DMAC_CTRLBx register.

b.

Set up the transfer characteristics, such as:

– i. Transfer width for the source in the SRC_WIDTH field.

– ii. Transfer width for the destination in the DST_WIDTH field.

– iii. Source AHB master interface layer in the SIF field where source resides.

– iv. Destination AHB master interface layer in the DIF field where destination resides.

– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.

– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.

3.

Write the channel configuration information into the DMAC_CFGx register for channel x.

a.

Designate the handshaking interface type (hardware or software) for the source and destination 
peripherals. This is not required for memory. This step requires programming the 
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking inter-
face to handle source/destination requests for the specific channel. Writing a ‘0’ activates the software 
handshaking interface to handle source/destination requests.

b.

If the hardware handshaking interface is activated for the source or destination peripheral, assign the 
handshaking interface to the source and destination peripheral. This requires programming the 
SRC_PER and DST_PER bits, respectively.

4.

Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are 
set as shown in Row 4 of 

. The LLI.DMAC_CTRLBx register of the last Linked List 

example with two list items.

5.

Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are 
non-zero and point to the base address of the next Linked List Item. 

6.

Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in mem-
ory point to the start source/destination buffer address preceding that LLI fetch.

7.

Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI 
entries in memory are cleared.