Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Data Sheet

 947

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

DMAC Transfer Flow for Source and Destination Address Auto-reloaded

1.

Read the Channel Enable register to choose a free (disabled) channel.

2.

Set up the chain of linked list items (otherwise known as buffer descriptors) in memory. Write the control 
information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers location of the buffer descriptor for 
each LLI in memory for channel x. For example, in the register you can program the following:

a.

Set up the transfer type (memory or non-memory peripheral for source and destination) and flow con-
trol peripheral by programming the FC of the DMAC_CTRLBx register.

b.

Set up the transfer characteristics, such as:

– i. Transfer width for the source in the SRC_WIDTH field.

– ii. Transfer width for the destination in the DST_WIDTH field.

– iii. Source AHB master interface layer in the SIF field where source resides.

– iv. Destination AHB master interface layer in the DIF field where destination resides.

– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.

– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.

3.

Write the starting source address in the DMAC_SADDRx register for channel x.

Note:

The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs) setup up in memory, 
although fetched during a LLI fetch, are not used.

Channel Enabled by

software

Buffer Transfer

Replay mode for SADDRx,

DADDRx, CTRLAx, CTRLBx

Channel Disabled by

hardware

Buffer Complete interrupt

generated here

HDMA Transfer Complete
Interrupt generated here

yes

no

yes

Stall until STALLED is cleared

by writing to KEEPON field

EBCIMR[x]=1

no

Is HDMA in Row1 of 

HDMA State Machine table