Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

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SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

The EBI I/Os accept two drive levels, HIGH and LOW. This allows to avoid overshoots and give the best performance 
according to the bus load and external memories.

The slew rates are determined by programming EBI_DRIVE bit in the EBI Chip Select Assignment Register 
(CCFG_EBICSA) in the Bus Matrix.

At reset the selected current drive is LOW. 

To reduce EMI, programmable delay has been inserted on high-speed lines. The control of these delays is as follows:



EBI (DDR2SDRC\SMC\NAND Flash)

D[15:0] controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface. 



D[0] <=> DELAY1[3:0], 



D[1] <=> DELAY1[7:4],...,



D[6] <=> DELAY1[27:24],



D[7] <=> DELAY1[31:28]



D[8] <=> DELAY2[3:0],



D[9] <=> DELAY2[7:4],...,



D[14] <=> DELAY2[27:24],



D[15] <=> DELAY2[31:28]

D[31:16] on PIOD[21:6] controlled by 2 registers, DELAY3 and DELAY4 located in the SMC user interface.



D[16] <=> DELAY3[3:0],



D[17] <=> DELAY3[7:4],...,



...



D[24] <=> DELAY4[3:0]



D[25] <=> DELAY4[7:4]



D[26] <=> DELAY4[11:8]



D[27] <=> DELAY4[15:12]



D[28] <=> DELAY4[19:16]



D[29] <=> DELAY4[23:20]



D[30] <=> DELAY4[27:24]



D[31] <=> DELAY4[31:28]

Note:

1.

A20, A23, A24 and A25 are multiplexed with D25, D26, D27 and D28 in PIOD, on PD15, PD16, PD17 and 
PD18 lines respectively. Delays applied on these IO lines are common to A20, A23, A24, A25 and D25, 
D26, D27, D28 respectively.

A[25:0], controlled by 4 registers DELAY5, DELAY6, DELAY7 and DELAY8 located in the SMC user interface.



A[0] <=> DELAY5[3:0] 



A[1] <=> DELAY5[7:4],..., 



...



A[14] <=> DELAY6[27:24]



A[15] <=> DELAY6[31:28]



A[16] <=> DELAY7[3:0]



A[17] <=> DELAY7[7:4]



A[18] <=> DELAY7[11:8]

and



A19 <=> DELAY7[15:12]



A21 <=> PD[2] <=> DELAY7[23:20]



A22 <=> PD[3] <=> DELAY7[27:24]