Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
337
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 26-3. NAND Flash and External RAM Not in Same Power Supply Range (NFD0_ON_D16 = 1)
At reset NFD0_ON_D16 = 0 and the NAND Flash bus is connected to D0–D15.
26.5.3.5 Static Memory Controller
For information on the Static Memory Controller, refer to the Static Memory Controller section of this datasheet.
26.5.3.6 DDR2SDRAM Controller
The product embeds a multi-port DDR2SDR Controller. This allows to use three additional ports on DDR2SDRC to
lessen the EBI load from a part of DDR2 or LP-DDR accesses. This increases the bandwidth when DDR2 and NAND
Flash devices are used. This feature is NOT compatible with SDR or LP-SDR Memory.
lessen the EBI load from a part of DDR2 or LP-DDR accesses. This increases the bandwidth when DDR2 and NAND
Flash devices are used. This feature is NOT compatible with SDR or LP-SDR Memory.
It is controlled by DDR_MP_EN bit in EBI Chip Select Assignment Register.
Figure 26-4. DDR2SDRC Multi-port Enabled (DDR_MP_EN = 1)
Figure 26-5. DDR2SDRC Multi-port Disabled (DDR_MP_EN = 0)
D[15:0]
ALE
A[22:21]
CLE
D[15:0]
EBI
NAND Flash (3.3V)
DDR2 or
LP-DDR or
16-bit LP-SDR (1.8V)
D[15:0]
D[31:16]
Bus Matrix
DDR2SDRC
Port 2
Port 1
Port 0
EBI
DDR2 or LP-DDR
Device
NAND Flash
Device
Port 3
Bus Matrix
DDR2SDRC
not used
not used
Port 0
EBI
(LP-)SDR
Device
NAND Flash
Device
not used