Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

338

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

For information on the PMECC Controller, refer to PMECC and PMERRLOC sections; also refer to Boot Strategies 
Section, NAND Flash Boot: PMECC Error Detection and Correction.

External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.

The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the 
EBI_CSA field in the EBI_CSA Register in the Chip Configuration User Interface to the appropriate value enables the 
NAND Flash logic.

 

For details on this register, refer to the Bus Matrix section. Access to an external NAND Flash device 

is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).

The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals 
when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the 
NCS3 address space. See 

 for more information. For details on these waveforms, refer to the 

Static Memory Controller section.

The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 
and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are 
distinguished by using their address within the NCSx address space. The chip enable (CE) signal of the device and the 
ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not 
selected, preventing the device from returning to standby mode.

D[7:0]

ALE

NANDWE

NANDOE

NOE

NWE

A[22:21]

CLE

AD[7:0]

PIO

R/B

EBI

CE

NAND Flash

PIO

NCSx/NANDCS

Not Connected