Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
211
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
18.8.1.3 Mode 2
Name:
CTRL
Offset:
0x00
Reset:
0x0000
Property:
Write-Protected, Enable-Protected, Write-Synchronized
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Bit
15
14
13
12
11
10
9
8
PRESCALER[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MATCHCLR
CLKREP
MODE[1:0]
ENABLE
SWRST
Access
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Table 18-8. Prescaler
PRESCALER[3:0]
Prescaler
Description
0x0
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x2
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x3
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x4
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x5
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x6
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x7
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x8
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0x9
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xA
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF
-
Reserved