Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
218
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
18.8.4.2 Mode 1
Name:
INTENCLR
Offset:
0x06
Reset:
0x00
Property:
Write-Protected
z
Bit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchroni-
zation Ready interrupt flag is set.
zation Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
interrupt.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – CMP1: Compare 1 Interrupt Enable
0: The Compare 1 interrupt is disabled.
1: The Compare 1 interrupt is enabled, and an interrupt request will be generated when the Compare 1 interrupt
flag is set.
0: The Compare 1 interrupt is disabled.
1: The Compare 1 interrupt is enabled, and an interrupt request will be generated when the Compare 1 interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare 1 Interrupt Enable bit and disable the corresponding interrupt.
Writing a one to this bit will clear the Compare 1 Interrupt Enable bit and disable the corresponding interrupt.
z
Bit 0 – CMP0: Compare 0 Interrupt Enable
0: The Compare 0 interrupt is disabled.
1: The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare 0 interrupt
flag is set.
0: The Compare 0 interrupt is disabled.
1: The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare 0 interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt.
Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt.
Bit
7
6
5
4
3
2
1
0
OVF
SYNCRDY
CMP1
CMP0
Access
R/W
R/W
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0