Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register 
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.

INTENSET

0x07

0x00

Write-Protected

z

Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.

1: The overflow interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.

z

Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.

1: The synchronization ready interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization 
Ready interrupt. 

z

Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.

z

Bit 0 – CMP0: Compare 0 Interrupt Enable
0: The compare 0 interrupt is disabled.

1: The compare 0 interrupt is enabled.

Writing a zero to this bit has no effect.

Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.

Bit

7

6

5

4

3

2

1

0

Access

R/W

R/W

R

R

R

R

R

R

Reset

0

0

0

0

0

0

0

0