Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

Product codes
ATSAMD20-XPRO
Page of 660
224
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
18.8.6.2  Mode 1
Name:
INTFLAG
Offset:
0x08
Reset:
0x00
Property:
-
z
Bit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag. 
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will 
be generated ifINTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
z
Bit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag. 
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY), 
except when caused by Enable or software Reset, and an interrupt request will be generated if INTEN-
CLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
z
, and an interrupt request will be generatedBits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to 
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – CMP1: Compare 1
This flag is cleared by writing a one to the flag. 
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt 
request will be generated if INTENCLR/SET.COMP1 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 1 interrupt flag.
z
Bit 0 – CMP0: Compare 0
This flag is cleared by writing a one to the flag. 
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt 
request will be generated if INTENCLR/SET.COMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.
Bit
7
6
5
4
3
2
1
0
OVF
SYNCRDY
CMP1
CMP0
Access
R/W
R/W
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0