Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
259
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
20.5
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described below.
20.5.1 Power Management
The NVMCTRL will continue to operate in any sleep mode where the selected source clock is running. The NVMCTRL’s
interrupts can be used to wake up the device from sleep modes. Refer to
interrupts can be used to wake up the device from sleep modes. Refer to
for details
on the different sleep modes.
The Power Manager will automatically put the NVM block into a low-power state when entering sleep mode. This is
based on the Control B register (CTRLB - refer to
based on the Control B register (CTRLB - refer to
for more details.
20.5.2 Clocks
Two synchronous clocks are used by the NVMCTRL. One is provided by the AHB bus (CLK_NVMCTRL_AHB) and the
other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of
wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the
NVM Controller is configured with the proper number of wait states. Refer to the
other is provided by the APB bus (CLK_NVMCTRL_APB). For higher system frequencies, a programmable number of
wait states can be used to optimize performance. When changing the AHB bus frequency, the user must ensure that the
NVM Controller is configured with the proper number of wait states. Refer to the
for the exact number of wait states to be used for a particular frequency range.
20.5.3 Interrupts
The NVM Controller interrupt request line is connected to the interrupt controller. Using the NVMCTRL interrupt requires
the interrupt controller to be programmed first.
the interrupt controller to be programmed first.
20.5.4 Debug Operation
When an external debugger forces the CPU into debug mode, the peripheral continues normal operation.
Access to the NVM block can be protected by the security bit. In this case, the NVM block will not be accessible. See
20.5.5 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
following registers:
z
Interrupt Flag Status and Clear register (INTFLAG - refer to
)
z
Status register (STATUS - refer to
Write-protection is denoted by the Write-Protected property in the register description. Write-protection does not apply for
accesses through an external debugger.
accesses through an external debugger.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Refer to
20.5.6 Analog Connections
Not applicable.
20.6
Functional Description
20.6.1 Principle of Operation
The NVM Controller is a slave on the AHB and APB buses. It responds to commands, read requests and write requests,
based on user configuration.
based on user configuration.