Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
260
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
20.6.2 Basic Operations
20.6.2.1 Initialization
After power up, the NVM Controller goes through a power-up sequence. During this time, access to the NVM Controller
from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user
configuration.
from the AHB bus is halted. Upon power-up completion, the NVM Controller is operational without any need for user
configuration.
20.6.2.2 Enabling, Disabling and Resetting
Not applicable.
20.6.3 Memory Organization
for memory sizes and addresses for each device.
The NVM is organized into rows, where each row contains four pages, as shown in
. The NVM has a row-
erase granularity, while the write granularity is by page. In other words, a single row erase will erase all four pages in the
row, while four write operations are used to write the complete row.
row, while four write operations are used to write the complete row.
Figure 20-2. Row Organization
The NVM block contains a calibration and auxiliary space that is memory mapped. Refer to
for details.
The calibration and auxiliary space contains factory calibration and system configuration information. This space can be
read from the AHB bus in the same way as the main NVM main address space.
read from the AHB bus in the same way as the main NVM main address space.
In addition, a boot loader section can be allocated at the beginning of the main array, and an EEPROM emulation area
can be allocated at the end of the NVM main address space.
can be allocated at the end of the NVM main address space.
Figure 20-3. NVM Memory Organization
The lower rows in the NVM main address space can be allocated as a boot loader section by using the BOOTPROT
fuses, and the upper rows can be allocated to EEPROM emulation, as shown in
fuses, and the upper rows can be allocated to EEPROM emulation, as shown in
. The boot loader section is
protected by the lock bit(s) corresponding to this address space and by the BOOTPROT[2:0] fuse. The EEPROM rows
can be written regardless of the region lock status. The number of rows protected by BOOTPROT and the number of
rows allocated to EEPROM emulation are given in
can be written regardless of the region lock status. The number of rows protected by BOOTPROT and the number of
rows allocated to EEPROM emulation are given in
, respectively.
Page (n * 4) + 0
Row n
Page (n * 4) + 1
Page (n * 4) + 2
Page (n * 4) + 3
NVM Base Address
Calibration and
auxiliary space
NVM Main
Address Space
NVM Base Address + NVM size
NVM Base Address + 0x00800000