Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
359
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.8.7 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x0E
Reset:
0x00
Property:
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – RXS: Receive Start
This flag is cleared by writing a one to it.
This flag is cleared by writing a one to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is one).
(CTRLB.SFDE is one).
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start interrupt flag.
z
Bit 2 – RXC: Receive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
z
Bit 1 – TXC: Transmit Complete
This flag is cleared by writing a one to it or by writing new data to DATA.
This flag is cleared by writing a one to it or by writing new data to DATA.
This flag is set when the entire frame in the transmit shift register has been shifted out and there are no new data
in DATA.
in DATA.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
z
Bit 0 – DRE: Data Register Empty
This flag is cleared by writing new data to DATA.
This flag is cleared by writing new data to DATA.
This flag is set when DATA is empty and ready to be written.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
Bit
7
6
5
4
3
2
1
0
RXS
RXC
TXC
DRE
Access
R
R
R
R
R/W
R
R/W
R
Reset
0
0
0
0
0
0
0
0