Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
360
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.8.8 Status
Name:
STATUS
Offset:
0x10
Reset:
0x0000
Property:
z
Bit 15 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z
Bits 14:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – BUFOVF: Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full,
there is a new character waiting in the receive shift register and a new start bit is detected.
there is a new character waiting in the receive shift register and a new start bit is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
z
Bit 1 – FERR: Frame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, i.e., when the first stop bit is zero.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
z
Bit 0 – PERR: Parity Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing a one to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is one) and a parity error is detected.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
Bit
15
14
13
12
11
10
9
8
SYNCBUSY
Access
R/W
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BUFOVF
FERR
PERR
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0