Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
37
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
12.
DSU – Device Service Unit
12.1
Overview
The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM Debug Access Port
(DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to
debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as
well as identification of other debug components in the system. Hence, it complies with the ARM Peripheral Identification
specification. The DSU also provides system services to applications that need memory testing, as required for
IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as
it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or
unavailable when the device is protected by the NVMCTRL security bit (refer to
(DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to
debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as
well as identification of other debug components in the system. Hence, it complies with the ARM Peripheral Identification
specification. The DSU also provides system services to applications that need memory testing, as required for
IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as
it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or
unavailable when the device is protected by the NVMCTRL security bit (refer to
12.2
Features
z
CPU reset extension
z
Debugger probe detection (Cold- and Hot-Plugging)
z
Chip-Erase command and status
z
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
z
ARM
®
CoreSight™ compliant device identification
z
Two debug communications channels
z
Debug access port security filter
z
Onboard memory built-in self-test (MBIST)
12.3
Block Diagram
Figure 12-1. DSU Bock Diagram
DSU
SWCLK
CORESIGHT ROM
DAP SECURITY FILTER
CRC-32
MBIST
CHIP ERASE
RESET
cpu_reset_extension
CPU
DAP
SWDIO
NVMCTRL
DBG
M
HIGH-SPEED
HIGH-SPEE
BUS MATRIX
MATR
US M
M
S
debugger_present
DEBUGGER PROBE
INTERFACE
AHB-AP
PORTMUX