Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
38
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
12.4
Signal Description
for details on the pin mapping for this peripheral.
12.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
12.5.1 I/O Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and the condition to stretch
the CPU reset phase. For more information, refer to
the CPU reset phase. For more information, refer to
. The Hot-Plugging feature
depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled,
the Hot-Plugging feature is disabled until a power-reset or an external reset.
the Hot-Plugging feature is disabled until a power-reset or an external reset.
12.5.2 Power Management
The DSU will continue to operate in any sleep mode where the selected source clock is running.
12.5.3 Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled in the Power Manager. For
more information on the CLK_DSU_APB and CLK_DSU_AHB clock masks, refer to
more information on the CLK_DSU_APB and CLK_DSU_AHB clock masks, refer to
.
12.5.4 Interrupts
Not applicable.
12.5.5 Events
Not applicable.
12.5.6 Register Access Protection
All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
following registers:
z
Debug Communication Channel 0 register (DCC0)
z
Debug Communication Channel 1 register (DCC1)
Write-protection is denoted by the Write-Protection property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to
12.5.7 Analog Connections
Not applicable.
Signal Name
Type
Description
RESET
Digital Input
External reset
SWCLK
Digital Input
SW clock
SWDIO
Digital I/O
SW bidirectional data pin