Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds, 
some peripheral accesses by the CPU needs to be synchronized between the different clock domains. In these cases the 
peripheral includes a SYNCBUSY status flag that can be used to check if a sync operation is in progress. As the nature 
of the synchronization might vary between different peripherals, detailed description for each peripheral can be found in 
the sub-chapter “synchronization” for each peripheral where this is necessary. 

In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while asynchronous clocks 
are clock generated by generic clocks.

All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a 
corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these 
clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes 
place even if the clocks domains are clocked from the same source and on the same frequency. All registers in the bus 
interface are accessible without synchronization. All core registers in the generic clock domain must be synchronized 
when written. Some core registers must be synchronized when read. Registers that need synchronization has this 
denoted in each individual register description. Two properties are used: write-synchronization and read-synchronization.

A common synchronizer is used for all registers in one peripheral, as shown in 

. Therefore, only one register 

per peripheral can be synchronized at a time.

SYSCTRL

DFLL48M

Generic Clock 
Generator 1

Generic Clock
Multiplexer 13

SERCOM 0

Main Clock

Controller

PM

GCLK_SERCOM0_APB

GCLK_SERCOM0_CORE

GCLK