Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

The write-synchronization is triggered by a write to any generic clock core register. The Synchronization Busy bit in the 
Status register (STATUS.SYNCBUSY) will be set when the write-synchronization starts and cleared when the write-
synchronization is complete. Refer to 

 for details on the synchronization delay. 

When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will cause the 
peripheral bus to stall until the synchronization is complete: 

z

Writing a generic clock core register

z

Reading a read-synchronized core register

z

Reading the register that is being written (and thus triggered the synchronization)

Core registers without read-synchronization will remain static once they have been written and synchronized, and can be 
read while the synchronization is ongoing without causing the peripheral bus to stall. APB registers can also be read 
while the synchronization is ongoing without causing the peripheral bus to stall.

Non Synced reg

INTFLAG

STATUS

READREQ

Write-Synced reg

Write-Synced reg

R/W-Synced reg

Synchronizer

Sync

SYNCBUSY

Synchronous Domain
       (CLK_APB)

Asynchronous Domain
          (generic clock)

Peripheral bus