Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

As indicated below, transfers are sequential events carried out on the USB bus.

Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 

2. Isochronous transfers must use endpoints with ping-pong attributes.
3. Control transfers can be aborted using a stall handshake.

A status transaction is a special type of host-to-device transaction used only in a control transfer. The control 

transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read 

or write), the USB device sends or receives a status transaction.

Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using 

DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol 

layer. 

CONTROL (bidirectional)

Control

Setup transaction → Data IN transactions → Status OUT transaction
Setup transaction → Data OUT transactions → Status IN transaction
Setup transaction → Status IN transaction

IN (device toward host)

Interrupt IN

Data IN transaction → Data IN transaction

Isochronous

 

IN

Bulk IN

OUT (host toward device)

Interrupt OUT

Data OUT transaction → Data OUT transaction

Isochronous OUT

Bulk OUT

Control Read

Setup TX

Data OUT TX

Data OUT TX

Data Stage

Control Write

Setup Stage

Setup Stage

Setup TX

Setup TX

No Data
Control

Data IN TX

Data IN TX

Status Stage

Status Stage

Status IN TX

Status OUT TX

Status IN TX

Data Stage

Setup Stage

Status Stage