Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx 

(TXPKTRDY must be cleared).

2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte 

values in the endpoint’s UDP_FDRx.

3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s 

UDP_CSRx.

4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in 

the endpoint’s UDP_CSRx has been set. Then an interrupt for the corresponding endpoint is pending while 

TXCOMP is set.

5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more 

byte values in the endpoint’s UDP_FDRx.

6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s 

UDP_CSRx.

7. The application clears the TXCOMP in the endpoint’s UDP_CSRx.

After the last packet has been sent, the application must clear TXCOMP once this has been set. 
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is 

pending while TXCOMP is set. 

TX_COMP must be cleared after TX_PKTRDY has been set.

Note:

Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol 

layer.

The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows 

handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a 

constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the 

current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the 

microcontroller, the other one is locked by the USB device.

USB Bus Packets

Data IN 2

Data IN

NAK

ACK

Data IN 1

FIFO (DPR)
Content

Data IN 2

Load In Progress

Data IN 1

Cleared by Firmware

DPR access by the firmware

Payload in FIFO

TXCOMP Flag
(UDP_CSRx) 

TXPKTRDY Flag
(UDP_CSRx)

PID

Data IN

Data IN

PID

PID

PID

PID

ACK

PID

Prevous Data IN TX

Microcontroller Load Data in FIFO

Data is Sent on USB Bus

Interrupt

Pending

Interrupt Pending

Set by the firmware

Set by the firmware

Cleared by

Firmware

Cleared by Hw

Cleared by Hw

DPR access by the hardware