Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

1102

The DACC uses the master clock (MCK) divided by two to perform conversions. 

This clock is named DACC clock.

 

Once a conversion starts, the DACC takes 

25 clock periods to provide the analog result on the selected analog 

output.

When a conversion is completed, the resulting analog value is available at the selected DACC channel output and 

the EOC bit in the 

 (DACC_ISR) is set.

Reading DACC_ISR clears the EOC bit.

In free-running mode, conversion starts as soon as at least one channel is enabled and data is written in the 

 (DACC_CDR). 

25

 DACC clock periods later, the converted data is available at the 

corresponding analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.

 Disabling the external trigger mode automatically sets the DACC in free-running mode.

A four half-word FIFO is used to handle the data to be converted.
If the TXRDY flag in the 

 (DACC_ISR) is active, the DAC controller is ready to 

accept conversion requests by writing data into the 

 (DACC_CDR). Data which 

cannot be converted immediately is stored in the DACC FIFO.
When the FIFO is full or when the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
The WORD field of the 

 (DACC_MR) allows the user to switch between half-word and word 

transfers in order to write into the FIFO.
In half-word transfer mode, only the 16 LSBs of DACC_CDR data are taken into account. DACC_CDR[15:0] bits 

are stored in the FIFO. DACC_CDR[11:0] bits are used as data. The DACC_CDR[15:12] bits are used for channel 

selection if the TAG field is set in DACC_MR register.
In word transfer mode, each time DACC_CDR is written, two data items are stored in the FIFO. The first data item 

sampled for conversion is DACC_CDR[15:0] and the second is DACC_CDR[31:16]. 
Bits DACC_CDR[15:12] and DACC_CDR[31:28] are used for channel selection if the TAG field is set in 

DACC_MR.

 Writing in DACC_CDR while TXRDY flag is inactive will corrupt FIFO data.

There are two ways to select the channel to perform data conversion.



By default, the USER_SEL field of the 

 (DACC_MR) is used. Data requests are 

converted to the channel selected with the USER_SEL field.



Alternatively, the tag mode can be used by setting the TAG field of the 

 (DACC_MR) to 

1. In this mode, the two bits, DACC_CDR[13:12], which are otherwise unused, are employed to select the 

channel in the same way as with the USER_SEL field. Finally, if the WORD field is set, the two bits, 

DACC_CDR[13:12] are used for channel selection of the first data and the two bits, DACC_CDR[29:28] for 

channel selection of the second data.