Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The DACC sleep mode maximizes power saving by automatically deactivating the DACC when it is not being used 

for conversions.
When a start conversion request occurs, the DACC is automatically activated. As the analog cell requires a start-

up time, the logic waits during this time and starts the conversion on the selected channel. When all conversion 

requests are complete, the DACC is deactivated until the next request for conversion.
A fast wake-up mode is available in the 

 (DACC_MR) as a compromise between power 

saving strategy and responsiveness. Setting the FASTW bit to 1 enables the fast wake-up mode. In fast wake-up 

mode, the DACC is not fully deactivated as long as no conversion is requested, thereby providing less power 

saving but faster wake-up (4 times faster).

The DACC start-up time must be defined by the user in the STARTUP field of the 

 

(DACC_MR).
The start-up time differs depending on the use of the fast wake-up mode with sleep mode. In this case, the user 

must set the STARTUP time corresponding to the fast wake-up and not the standard start-up time.
A maximum speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. In this mode, the DAC 

Controller no longer waits to sample the end-of-cycle signal coming from the DACC block to start the next 

conversion. An internal counter is used instead, thus gaining two DACC clock periods between each consecutive 

conversion.

 If the maximum speed mode is used, the EOC interrupt of DACC_IER should not be used as it is two 

DACC Clock periods late.
The accuracy of the analog voltage resulting from the data conversion process cannot be guaranteed due to 

leakage. To ensure accuracy, the channel must be refreshed on a regular basis. A value is correctly refreshed if 

the correct sampling period is selected (see DACC electrical characteristics) and the software or PDC is able to 

sustain writing to DACC_CDR at the rate imposed by the trigger period. 
Note that the DACC is able to automatically refresh the converted value without CPU intervention.
When REFRESH field in the DACC_MR is written to 1, the automatic refresh period is enabled for the analog 

channels.
Warning:

 A REFRESH field set to 0 will disable the automatic refresh function of the DACC channels.