Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet

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SAM4S Series [DATASHEET]

Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14

The errata are applicable to the devices in 

If one of the subsectors 



small sector 0



small sector 1



larger sector

is locked within the Flash sector 0, the erase sector (ES) command cannot be processed on non-locked subsectors. 

Refer to the Flash overview in the “Memories” section of the datasheet.

All the lock bits of the sector 0 must be cleared prior to issuing the ES command. After the ES command has been 

issued, the lock bits must be reverted to the state before clearing them.

Flash read issues leading to wrong instruction fetch or incorrect data read may occur under the following operating 

conditions:
VDDIO < 2.4V and Flash wait state

 ≥ 1

If the core clock frequency does not require the use of the Flash wait state 

 (FWS = 0 in EEFC_FMR) or if only data 

reads are performed on the Flash (e.g., if the code is running out of SRAM), there are no constraints on VDDIO voltage. 

 .

Notes:

1. Defined by the FWS field in EEFC_FMR register.
2. See 

 for the maximum core clock frequency at zero (0) wait 

state.

Two workarounds are available:

1. Reduce the device speed to decrease the number of wait states to 0.
2. Copy the code from Flash to SRAM at 0 wait states and then run the code out of SRAM.

The issue will be corrected in the next device revision, Marketing Revision Level B (MRL B). Please contact your local 

Sales Representative for further details.

SAM4S4C (Rev A)

0x28AB_09E0

SAM4S4B (Rev A)

0x289B_09E0 

SAM4S4A (Rev A) 

0x288B_09E0

SAM4S2C (Rev A)

0x28AB_07E0

SAM4S2B (Rev A)

0x289B_07E0 

SAM4S2A (Rev A)

0x288B_07E0